Design of custom ASICs, SOC and FPGA

Specialties & Experience of this Expert Witness

Additional Information

Strong technical and business leader entire Digital Design and chip integration flow. Proven track record of managing dispersed and efficient teams and delivering successful silicon and system success in large and small company environments ASIC SOC FPGA systems including memory controllers SDRAM DDR high speed communication interfaces PCIe SATA USB wireless devices peripherals 10Gb Xaui XFI Memory controllers SRAM DRAM DDR protocols and designs Cryptography FEC Forward Error Correction MAC Media Access Controller for DOCSIS 802.11 Intel ARM AHB bus AXI AHB APB Power PC MIPS microprocessor architectures GPU architectures and chipsets MCU integration PCI USB Ethernet LIDAR sensor MIPI AI systems and processors development tools C/C++ Pascal Java JavaScript PLI development Perl Python Typescript HTML Go Tcl Cell3 Virtuoso, Formality/LEC Custom IC design tools. bitcoin blockchain async logic IOT Internet of Things Telecommunication computer network broadband TCP/IP UDP DNS Object oriented design and programming wifi firmware hardware circuit IT repository CVS SVN USB-C storage devices motherboard UART electronics state machine code review source code data communication routing network high frequency systems RISC-based CISC processor optimizing memory performance with opportunistic refreshing Queue Wireless computer system with queue and scheduler asynchronous circuits and systems buffered DRAM technology Plug and play display connection using VESA ECC Error Correction Code microcode clock x86 FPU multiplier adder lab debug physical design timing closure SPI4 switch chip architecture prototyping throughput latency switching LAN WAN QOS quality of service queuing artificial intelligence embedded systems I/O BIOS personal computer low power management semiconductor transistor Microelectronics Electronic Instrumentation databases optical fiber switch RF Radio Frequency Signals infringement validity issues software source code hardware software split HDL code Verilog and VHDL patent infringement Examine schematics ASIC FPGA architecture design verification physical implementation PCS/TL/MAC layer for Ethernet PCIe SATA Memory DDR3 Flash NAND and NOR MRAM controller design and verification Smart Meter ASIC architecture and design including wireless communication solution NFC Near Field Communication 60GHZ wireless high bandwidth USB solution. Security cryptography IP development and integration 10/40/100G MLG GBOX ethernet repeater AHB2AXI and AXI2AHB bridges on-chip networks Communication protocols USB PCIe SATA PCI I2C HDMI CSI DP AUX SPI MIPI JTAG SOC System On Chip architecture IC Integrated Circuit smart meter RFID switch/networking/compute centric chips NOC Network on Chip architecture Project flow methodology review IP code re-usability Verification integration of cryptography IP AMD Cerebras Impinj Indie Semi Keyssa NetApp Netspeed PMC Sierra Rambus Silicon Chip low latency layer 2 24 port 1/10Gb Ethernet switch (200ns latency, 240Gb throughput layer 3 switch production board prototyping and reference design digital logic architecture and implementation IP relationships backend vendor selection and management Lead architecture and implementation Synchronous blocks SPI4 switch chip. chip’s development architecture design verification P+R test UVM system verilog universal verification methodology Xilinx FPGAs ASICs SoCs NOC Processors GPUs Chipset Programming Language Interface PLI Direct Programming Interface DPI Verilog Procedural Interface VPI Linux UNIX Windows Programming languages C C++ Scripting languages Bash Csh Tcl EDA tools Cadence Xilinx Vivado Altera Quartus Simulation EDA tools Electronic Design Automation Synopsys VCS Cadence Modelsim/Questa Logic equivalency synthesis SystemVerilog UVM Synopsys DC Synthesis Primetime PrimePower Synplicity FPGA